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Talent Scout

K

Kamil Jeziorek

AGH University of Krakow

P

Piotr Wzorek

AGH University of Krakow

K

Krzysztof Błachut

AGH University of Krakow

H

Hiroshi Nakano

Keio University

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References (51)

[1]
Event-based Audio Prediction with Spectro-Temporal Event-Graphs
2025Lars Rafeldt, Thomas Mesquida et al.
[2]
Scaling Up Resonate-and-Fire Networks for Fast Deep Learning
2025Thomas E. Huber, Jules Lecomte et al.
[3]
Automatic Speech Recognition: A survey of deep learning techniques and approaches
2025Harsh Ahlawat, Naveen Aggarwal et al.
[4]
TSkips: Efficiency Through Explicit Temporal Delay Connections in Spiking Neural Networks
2024Prajna G. Malettira, Shubham Negi et al.
[5]
FPGA-Based Hardware Acceleration for Deep Learning in Mobile Robotics
2024Yasir Al-Ameri, Ming Nguyen et al.
[6]
Event-Based Vision on FPGAs - a Survey
2024T. Kryjak
[7]
Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs
2024K. Jeziorek, Piotr Wzorek et al.
[8]
High Accuracy and Low Latency Mixed Precision Neural Network Acceleration for TinyML Applications on Resource-Constrained FPGAs
2024Wei Soon Ng, Wangling Goh et al.
[9]
EvGNN: An Event-Driven Graph Neural Network Accelerator for Edge Vision
2024Yufeng Yang, Adrian Kneip et al.
[10]
Scalable Event-by-Event Processing of Neuromorphic Sensory Signals with Deep State-Space Models
2024Mark Schöne, Neeraj Mohan Sushma et al.
[11]
A Fully-Configurable Open-Source Software-Defined Digital Quantized Spiking Neural Core Architecture
2024Shadi Matinizadeh, Noah Pacik-Nelson et al.
[12]
17.8 0.4V 988nW Time-Domain Audio Feature Extraction for Keyword Spotting Using Injection-Locked Oscillators
2024A. Mostafa, Emmanuel Hardy et al.
[13]
DenRAM: Neuromorphic Dendritic Architecture with RRAM for Efficient Temporal Processing with Delays
2023Simone DAgostino, Filippo Moro et al.
[14]
TinyML Acoustic Classification using RAMAN Accelerator and Neuromorphic Cochlea
2023Adithya Krishna, H. Shankaranarayanan et al.
[15]
Learnable axonal delay in spiking neural networks improves spoken word recognition
2023Pengfei Sun, Yansong Chua et al.
[16]
Memory-Efficient Graph Convolutional Networks for Object Classification and Detection with Event Cameras
2023K. Jeziorek, A. Pinna et al.
[17]
Learning Delays in Spiking Neural Networks using Dilated Convolutions with Learnable Spacings
2023Ilyass Hammouamri, Ismail Khalfaoui Hassani et al.
[18]
Low-Power Event-Driven Spectrogram Extractor for Multiple Keyword Spotting: A proof of concept
2023Soufiane Mourrane, Benoît Larras et al.
[19]
HUGNet: Hemi-Spherical Update Graph Neural Network applied to low-latency event-based optical flow
2023Thomas Dalgaty, Thomas Mesquida et al.
[20]
Are SNNs Really More Energy-Efficient Than ANNs? an In-Depth Hardware-Aware Study
2023Manon Dampfhoffer, T. Mesquida et al.

Showing 20 of 51 references

Founder's Pitch

"Develop a low-power, low-latency hardware-accelerated event-graph neural network for real-time audio classification and keyword spotting on FPGA."

Hardware-Accelerated AIScore: 7View PDF ↗

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2.5

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10

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5

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Why It Matters

This research is crucial for efficiently processing increasing data volumes from edge devices like smartwatches, where power and latency constraints are significant. It allows for efficient, real-time audio processing using event-based systems, which is increasingly relevant with the rise of IoT devices.

Product Angle

The technology can be productized as a hardware chip or a module integrated into smart devices, enabling offline and real-time audio processing without high energy consumption.

Disruption

This technology can replace traditional microphone and GPU-based audio processing systems, offering more efficient, energy-saving solutions.

Product Opportunity

The market for low-power audio processing chips is growing alongside IoT development, particularly in smart home devices, wearables, and mobile robotics. Companies making these devices would buy the technology to integrate into their products, improving efficiency and user experience.

Use Case Idea

Create a low-power audio processing chip for smart home devices to recognize user commands quickly and efficiently.

Science

The paper presents a method for implementing event-graph neural networks on FPGAs to process audio in real-time. An artificial cochlea converts audio signals into sparse event data, which then undergoes graph convolution and recurrent sequence modeling for keyword spotting tasks. This allows for low-power and low-latency operations crucial for edge devices.

Method & Eval

The implementation was tested on FPGA using SHD and SSC datasets for speech recognition tasks. It showed comparable accuracy to state-of-the-art neural networks but used significantly fewer resources.

Caveats

FPGA implementations might lack the flexibility of software-based solutions and could be limited by the scalability challenges inherent to hardware-based approaches.

Author Intelligence

Kamil Jeziorek

AGH University of Krakow
kjeziorek@agh.edu.pl

Piotr Wzorek

AGH University of Krakow
pwzorek@agh.edu.pl

Krzysztof Błachut

AGH University of Krakow
kblachut@agh.edu.pl

Hiroshi Nakano

Keio University
nakano@west.sd.keio.ac.jp

Manon Dampfhoffer

CEA-List, Université Grenoble Alpes
Manon.DAMPFHOFFER@cea.fr

Thomas Mesquida

CEA-List, Université Grenoble Alpes
thomas.mesquida@cea.fr

Hiroaki Nishi

Keio University
west@keio.jp

Thomas Dalgaty

CEA-List, Université Grenoble Alpes
Thomas.DALGATY@cea.fr

Tomasz Kryjak

AGH University of Krakow
kryjak@agh.edu.pl