Papers
1–3 of 3Research Paper·Mar 8, 2026
Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques
Modern applications process massive data volumes that overwhelm the storage and retrieval capabilities of memory systems, making memory the primary performance and energy-efficiency bottleneck of comp...
7.0 viability
Research Paper·Mar 4, 2026
Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators
Software-hardware co-design is essential for optimizing in-memory computing (IMC) hardware accelerators for neural networks. However, most existing optimization frameworks target a single workload, le...
5.0 viability
Research Paper·Jan 20, 2026
'1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators
Interconnect power consumption remains a bottleneck in Deep Neural Network (DNN) accelerators. While ordering data based on '1'-bit counts can mitigate this via reduced switching activity, practical h...
2.0 viability