State of Hardware Optimization

3 papers · avg viability 4.7

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Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques(7.0)
Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators(5.0)
'1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators(2.0)