Hardware Optimization Comparison Hub
3 papers - avg viability 4.7
Top Papers
- Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques(7.0)
Optimize memory access in existing processors by applying lightweight machine learning to learn access patterns and predict off-chip memory requests.
- Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators(5.0)
Develop a co-optimization framework for designing generalized in-memory computing accelerators that efficiently support multiple neural network workloads.
- '1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators(2.0)
Develop a hardware sorting unit to cut power usage in DNN accelerators by reducing HVAC needs.